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3.1.4 | INSTRUCTION SET
01 | THE CPU’S AVAILABLE COMMANDS
An instruction set is the complete collection of machine-code instructions a CPU can execute.
The CPU does not invent an operation when it meets an unfamiliar instruction. Its design determines which instructions it recognises and what each one does.
A program uses instructions from that set in a particular sequence. The instruction set is the available vocabulary; the program is a sequence written using that vocabulary.
02 | MACHINE CODE AND READABLE LABELS
The instructions executed by a CPU are machine code, represented in binary. For learning, we use readable labels such as LOAD, ADD and STORE.
These labels are called mnemonics when used as symbolic names for machine instructions. Assembly language uses such names; an assembler translates them into the appropriate machine code.
The CPU does not directly execute the English word “ADD”. It recognises the machine-code encoding defined by its instruction set.
Exact names and encodings vary between processors. The small instruction set below is invented for teaching, not an actual commercial CPU or the Cambridge pseudocode language.
03 | WHAT CAN INSTRUCTIONS DO?
| Type of operation | Teaching example | Purpose |
|---|---|---|
| Data transfer | LOAD 20 | Copy memory[20] into ACC |
| Arithmetic | ADD 21 | Add memory[21] to ACC |
| Data transfer | STORE 22 | Copy ACC into memory[22] |
| Comparison | COMPARE 23 | Compare a working value with another value |
| Control flow | JUMP 100 | Change the next instruction address |
| Input / output | INPUT or OUTPUT | Exchange data with the input/output system |
Not every instruction performs arithmetic. An instruction may move a value, test a condition or change which instruction runs next.
The ALU carries out arithmetic and logic; the control unit decodes instructions and coordinates execution. Instruction sets connect directly to the fetch–decode–execute cycle.
04 | OPERATION AND OPERAND
An instruction typically identifies an operation and may include information about a value, register or address to use.
| Teaching instruction | Operation | Operand meaning |
|---|---|---|
| LOAD 20 | Load ACC | Read the contents at memory address 20 |
| ADD 21 | Add to ACC | Use the contents at memory address 21 |
| STORE 22 | Store ACC | Write the value to memory address 22 |
The machine-code part specifying the operation is an opcode. An operand supplies information the operation uses. These terms help explain the examples; the core syllabus requirement is the purpose and use of an instruction set.
Operand meaning depends on the instruction format. It could be an address, a register or an immediate value. Do not assume every instruction has exactly one operand.
04A | START WITH AN ORDINARY INSTRUCTION
Imagine telling someone: “Add the number in box 21 to your running total.” This instruction contains two essential pieces of information:
- What to do: add.
- What to use: the number stored in box 21.
The CPU needs the same distinction, expressed in a format it recognises. In our model, the complete instruction is ADD 21. ADD names the operation; 21 tells it where to find the value to use.
An instruction is the complete command. The opcode and operand are parts of that command, not two separate instructions.
04B | THREE WORDS, THREE LEVELS
WHOLE INSTRUCTION: ADD 21
OPERATION PART: ADD
What operation should happen?
OPERAND PART: 21
Which location supplies the value?
Instruction: the complete command to execute.
Opcode: the encoded part of the machine instruction specifying the operation. ADD is its readable symbolic name, not its actual binary encoding.
Operand: information the operation needs. For this instruction it is the address 21. The value stored there is the operand data used in the addition.
If memory[21] contains 8, the instruction means “add 8”, not “add 21”. The CPU must access the specified location to obtain that 8.
04C | SEE A POSSIBLE BINARY FORMAT
Invent a simple format with four opcode bits followed by eight operand bits. In this invented instruction set, suppose ADD has opcode 0010.
| Opcode field: 4 bits | Operand field: 8 bits |
|---|---|
| 0010 | 00010101 |
| Meaning: ADD | Meaning: memory address 21 |
The complete machine instruction is 0010 00010101. The space is only a visual separator.
The CPU’s instruction-set design defines that 0010 means ADD and that the following eight bits supply a memory address for this format. The bits do not explain their own meaning.
A different processor could assign a different opcode or use different field sizes. Some instructions have no explicit operand, several operands, or fields identifying registers. Learn the distinction rather than memorising this invented encoding.
04D | FOLLOW THE COMPLETE PROCESS
Before execution: ACC = 12 and memory[21] = 8. The current instruction is ADD 21.
- Fetch the instruction: the CPU obtains the encoded instruction from the program’s memory location and keeps it in CIR.
- Decode the opcode: the control unit recognises the operation as ADD.
- Interpret the operand field: for this instruction format, 21 is the address of the value to use.
- Fetch the operand data: place address 21 in MAR, request a memory read and receive the value 8 in MDR.
- Perform the operation: the ALU adds the existing ACC value 12 to the operand data 8.
- Keep the result: ACC becomes 20. The instruction has now been executed.
Notice the two different reads: first read the instruction; later read the data named by the instruction. Address 21 selects the data, but it is not the data value.
The accumulator is an implicit input and destination in our ADD instruction. It does not have to be written as a second operand because this model’s instruction definition already specifies it.
04E | CHANGE ONE PART AND PREDICT THE EFFECT
| Instruction | What changed? | Effect |
|---|---|---|
| ADD 21 | Baseline | ACC becomes 12 + 8 = 20 |
| ADD 22 | Operand address changed | ACC becomes 12 + 3 = 15 |
| LOAD 21 | Operation changed | ACC becomes 8, replacing its previous value |
Keeping ADD but changing the operand selects a different value. Keeping address 21 but changing ADD to LOAD uses the same value in a different way.
If the contents at address 21 change from 8 to 10, ADD 21 produces 22 from an initial ACC of 12 even though the instruction itself is unchanged.
04F | ADD A VALUE OR ADD WHAT IS AT AN ADDRESS?
Operand interpretation is part of the instruction’s rules. It does not always mean a memory address.
- Our ADD 21: use the contents at address 21, which are 8.
- An invented ADDI 21: use the immediate value 21 itself, so an initial ACC of 12 would become 33.
ADDI is introduced only as an illustration of an immediate operand. It is not part of the three-instruction interactive model below. A real instruction set may use different names or encoding fields to distinguish these cases.
Ask: what does this instruction’s definition say the operand represents? That rule tells you whether to use a literal value, a register or a memory location.
05 | TRACE A COMPLETE SMALL PROGRAM
The program below adds two values and saves the result. Initially memory[20] = 12, memory[21] = 8 and memory[22] = 0.
| Program address | Instruction | Effect |
|---|---|---|
| 100 | LOAD 20 | ACC becomes 12 |
| 101 | ADD 21 | ACC becomes 12 + 8 = 20 |
| 102 | STORE 22 | memory[22] becomes 20 |
The instructions and data occupy locations in the same main memory in the Von Neumann model. Their roles differ: instructions specify operations; the values 12 and 8 are the data processed.
Changing memory[20] changes the result without changing the instructions. Reordering the instructions can change the result even when the input data stays the same.
06 | STEP THROUGH THE PROGRAM
This model shows each instruction’s overall effect. One click represents a completed instruction, not one clock cycle or the individual register transfers of fetch–decode–execute.
Ready: ACC = 0; memory[20] = 12; memory[21] = 8; memory[22] = 0.
Next instruction: LOAD 20.
The three-instruction demonstration ends after STORE. Real programs use defined control flow and termination behaviour.
07 | A SET IS NOT A PROGRAM
The instruction set includes the operations a CPU supports. A particular program may use only a small selection of those operations and may repeat them many times.
For example, a loop may use the same addition instruction repeatedly with different data. The CPU does not need a unique instruction called “calculate every student’s total”. The software combines smaller operations.
A larger instruction set is not automatically a faster or better CPU. Performance also depends on processor design, workload, memory access and the implementation of each instruction.
08 | WHY MACHINE CODE DEPENDS ON THE CPU
A binary encoding has meaning because a particular CPU’s instruction set defines it. Different processor families can use different encodings or support different operations.
Therefore machine code written for one instruction-set architecture is not automatically executable on another. Compatible processors may share an instruction set, but differences in features and the wider software platform can still matter.
High-level source code can be translated for a target system by suitable tools. That is different from assuming one compiled machine-code program works unchanged on every processor.
09 | LINK IT BACK TO THE CPU
- The CPU fetches the encoded instruction from memory.
- The control unit decodes the operation and operand information.
- The CPU carries out the required transfers, arithmetic or control action.
- The next instruction is selected, and the process repeats.
For ADD 21, the CPU needs the instruction and the operand data. The instruction tells it to add; address 21 tells it where this model’s operand is stored.
For a full register-level trace, revisit components of the CPU and the FDE model.
10 | COMMON MISTAKES
- Instruction set = one program: the set is the supported vocabulary; a program is a sequence.
- Machine code = English commands: readable names stand for binary encodings.
- LOAD 20 means load value 20: in this example it loads the contents at address 20.
- Every instruction is addition: transfer, logic and control operations also exist.
- One click equals one clock cycle: the demonstration groups an instruction’s effect.