3.1.2 | THE FETCH DECODE EXECUTE CYCLE

Topics from the Cambridge IGCSE (9-1) Computer Science 0984 syllabus 2023 - 2025.

OBJECTIVES
​3.1.2(a) Understand the purpose of the components in a CPU, in a computer that has a Von Neumann architecture
Including:
– units: arithmetic logic unit (ALU) and control unit (CU)
– registers: program counter (PC), memory address register (MAR), memory data register (MDR), current instruction register (CIR) and accumulator (ACC)
– buses: address bus, data bus and control bus

3.1.2(b) Describe the process of the fetch–decode–execute cycle including the role of each component in the process.
• How instructions and data are fetched from random access memory (RAM) into the CPU, how they are processed using each component and how they are then executed
• Storing data and addresses into specific registers
• Using buses to transmit data, addresses and signals
• Using units to fetch, decode and execute data and instructions

ALSO IN THIS TOPIC
 3.1.1 COMPUTER ARCHITECTURE 
YOU ARE HERE | 3.1.2 COMPUTER ARCHITECTURE 
3.1.3 COMPUTER ARCHITECTURE 
3.1.4 COMPUTER ARCHITECTURE(CIE) 
3.1.5 COMPUTER ARCHITECTURE 
3.2.1 INPUT AND OUTPUT DEVICES 
3.2.2 INPUT AND OUTPUT DEVICES 
3.2.3 INPUT AND OUTPUT DEVICES
3.3 DATA STORAGE 
3.4 NETWORK HARDWARE 
REVISION CARDS
TOPIC 3 KEY TERMINOLOGY
TOPIC 3 ANSWERS
TOPIC 3 TEACHER RESOURCES
TOPIC 1 TEACHER RESOURCES (CIE)

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VON NEUMANN MODEL

Whilst there are many different types of computer architecture in current technology, John von Neumann was a pioneer of the principle that modern processors follow.  This section closely relates to the basic Von Neumann concept of CPU architecture.

THE SYSTEM BUS

The system bus refers to the method in which data and signals are transferred throughout a computer system.​ Data travels through various medium such as cables, ribbons and tracks on a circuit board. Where processor fundamentals are concerned there are three different Bus systems each with their own purpose.

• The Address Bus
• The Data Bus
• The Control Bus

THE ADDRESS BUS
The address bus, as its name suggest simply carries an address. This address is the address(location) that needs to be accessed from the memory. If we think of the memory as being like a very large spreadsheet containing thousands of cells and each cell has its own unique address. The address bus carries the address location of a specific cell within the memory to be accessed. Earlier computers had address buses that were only 8 wires wide, this only allowed the machine to transfer 1 byte (8 bits) at a time, which limited the maximum amount of address locations that could be represented to 256 locations (with 1 byte we can represent between 0 and 255), so adding more that 256 memory locations to an 8 bit computer would have been very inefficient.

Many modern computers are 64 bit, meaning the address bus is 64 wires wide, allowing address locations of between 0 and 18,446,744,073,709,551,615 (18 Quintillion) to be accessed in a single request, although modern computers may not contain this amount of memory locations.

The Address Bus is unidirectional, meaning it is a one way system and only carries the location of the address to be accessed from the processor to the memory, the data from that memory location is then transfers through the Data Bus.

THE DATA BUS
THE Data Bus is bi-directional (meaning that data can flow two ways) and is responsible for transporting data between the memory, the processor and and I/O (input/output) devices. The size of the Data Bus varies between machines, however it is efficient to have a Data Bus at least equivalent to the size of a Word. A word is the number of bytes that the system will handle in one go, for example 16, 32 or 64 bits. If the computer system uses 64 bits as a word and the Data Bus is only 32 wires wide, then the word would need to be transmitted through the data bus as 2 separate signals, thus making it inefficient. The size of the Data Bus does not need to be the same size as the Address Bus.
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THE CONTROL BUS
The Control Bus is bi-directional (meaning that data can flow two ways) and is responsible for transmitting signals between various components. The Control Bus is generally only 8 wires wide as it carries signals rather than larges combinations of data representations. It is primarily tasked with carrying timing signals from the system clock, aiding the synchronisation of tasks.

The clock speed is a major factor in determining the overall speed of the computer, it can be seen that on every tick of the clock an action is performed, the more times per second the clock ticks the more actions are performed. 

As can be seen in the system bus diagram the Data Bus is not directly connected to any input or output devices, it is connected to a separate I/O interface or device controller.

1: Why is the address bus uni-directional?
2: How does the width of the address bus effect the access of memory locations?
3: What is the purpose of the Data bus? 
4: Why is the data bus a serial bus rather than a parallel bus? 
5: State the purpose of the control bus.

THE CENTRAL PROCESSING UNIT

The Central Processing Unit, CPU could be recognised as the brains of the computer, this is where most of the calculations and controlling takes place. CPUs work extremely fast and hard, a bi-product of this is that they generate a lot of heat, older CPUs used to sit under a large heat sink with a fan blowing air over the heat sink blades to dissipate the heat, however more modern CPUs no longer require this.

The main components of the CPU are the Arithmetic and Logic Unit, ALU and the registers.

The Arithmetic and Logic Unit is responsible for calculations such as addition, multiplication and logic such as AND and OR. Registers are temporary storage areas used to store small instructions or small pieces of data as it is being processed. Registers are very small and very fast memory situated very close to the ALU. The basic Von Neumann architecture comprises of the following registers.

• PC Program Counter
• MAR Memory Address Register
• MDR Memory Data Register ( Sometimes abbreviated as MBR)
• CIR Current Instruction Register
• IR Index Register (Sometimes abbreviated as IX)
• SR Status Register

PC Program Counter
Stores the memory address that holds the next instruction to be read. The incrementor increments/changes the program counter from one instruction to the next and the incrementor is controlled by the clock through the control unit. 

MAR Memory Address Register
The MAR holds the memory location address that is about to be written or read from

MDR Memory Data Register
The MDR, sometimes known as MBR (Memory Buffer Register) holds the data that has just been read, or the data that is about to be stored in a memory location.
​
CIR Current Instruction Register
The CIR is used to store the current instruction during the time it is being processed (decoded and executed).

IR Index Register
The IR is used to store the value of the current index being accessed. Used when accessing array variable, by indexing the address to be accessed a loop can be used to iterate the value of the index to be accessed. This is illustrated in the assembly language section.

The fetch decode execute cycle
The fetch execute cycle is used to describe the flow of data through the processor, how the data is fetched from memory, decoded, a decision on what to do with the data, and then executed, the appropriate action is carried out on the data.

The  fetch decode execute sequence
1: The value from the program counter is copied to the MAR
2: A request is made to retrieve the data from the memory location stipulated in the MAR, the request is send via the address bus(one way).
3: The content of the memory location is sent via the Data Bus to the MDR
4: A copy of the MDR is made and placed in the CIR
5: The value of the CIR is decoded (A decision made on what needs to be done with the data).
6: The data is moved to the Acc to be executed
7: A check for interrupts is made
8: The program counter is iterated.
Note: The program counter can be iterated at any point after the data is accessed from the memory location, stage 3, however for the purpose of this illustration it is iterated lastly.
9: The loop starts again.

​1: What are 'registers' ?
2: What is the role of 'interrupts' ?
3: Why does the CIR create a copy of the MDR?
​4: Describe what happens in the fetch stage of the cycle.
5: Describe what happens in the decode stage of the cycle.
​6: Describe what happens in the execute stage of the cycle.
7: Describe the role of the control unit during the Fetch decode execute cycle.

ADDITIONAL TASK
Sketch a visualisation of the internal operations of the CPU

WANT MORE HELP ON THE CPU? TRY THESE:
For a video showing the fetch decode execute cycle, click here (HurrayBanana, Published on Oct 11, 2013)
For a video that covers different types of addressing and the practical use, click here (Kevin Drumm, Published on Nov 27, 2018)
​Try Little Man Computing LMC - A simulation of the CPU
Try schweigi Github CPU simulation
Simple animation of the fetch decode execute cycle - by future learn

ALSO IN THIS TOPIC

3.1.1 COMPUTER ARCHITECTURE | The role of the CPU
3.1.2 COMPUTER ARCHITECTURE | Components of the CPU
3.1.3 COMPUTER ARCHITECTURE | Core's, Cache and Clock speed
3.1.4 COMPUTER ARCHITECTURE(CIE) | The Instruction Set
3.1.5 COMPUTER ARCHITECTURE | Embedded Systems
3.2.1 INPUT AND OUTPUT DEVICES | Input Devices
3.2.2 INPUT AND OUTPUT DEVICES | Output Devices
3.2.3 INPUT AND OUTPUT DEVICES | Sensors
3.3 DATA STORAGE | Primary, Secondary, Virtual and Cloud storage
3.4 NETWORK HARDWARE | Networks, Components and Protocols
REVISION CARDS | Flip cards to help test yourself
TOPIC 3 KEY TERMINOLOGY
TOPIC 3 ANSWERS
TOPIC 3 TEACHER RESOURCES