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10 | USING LOGIC GATES
01 | A CIRCUIT IS A CONNECTED RULE
A gate receives input signals and produces an output. When gates are connected, the output from an earlier gate becomes an input to a later gate. This lets several small rules describe one complete decision.
Consider a demonstration access indicator. It lights when a student has permission and the room is open, or when a blocking signal is not active. We will use this as a Boolean model, not a real security system.
A logic circuit shows the connected gates. A Boolean expression writes the same rule using names and operations. A truth table records the outcome for every possible input combination. Learn to move between all three.
02 | DEFINE WHAT EACH INPUT MEANS
For our example, A = 1 means PermissionPresent, B = 1 means RoomOpen, and C = 1 means BlockingSignalActive. X = 1 means IndicatorOn.
The first route needs both permission and an open room: A AND B. The second route needs the blocking signal to be absent: NOT C. Either route enables the indicator, so combine them with OR.
The expression is X = (A AND B) OR (NOT C). Each input is a proposition with a clearly defined true state. If C instead meant BlockingSignalAbsent, the second route would use C rather than NOT C.
03 | DRAW THE EXPRESSION AS THREE GATES
Start with the parts inside parentheses. Connect A and B to a two-input AND gate. Feed C to a one-input NOT gate. Send the two results into a two-input OR gate, which produces X.
We have labelled the intermediate signals P and Q. P is the result of A AND B; Q is the result of NOT C. They are not extra independent inputs: once A, B and C are chosen, P and Q are determined.
The complete circuit has three external inputs and one final output. The two-input OR gate receives P and Q, not all three external signals at once.
04 | FOLLOW ONE CASE THROUGH THE WIRES
Set A = 1, B = 0 and C = 1. The AND gate receives 1 and 0, therefore P = 0. The NOT gate receives 1, therefore Q = 0. The final OR receives 0 and 0, so X = 0.
Keep the intermediate result separate from the external input. The final gate does not receive C directly; it receives Q, which is the inverted value of C.
| Stage | Inputs used | Result |
|---|---|---|
| P = A AND B | 1 AND 0 | P = 0 |
| Q = NOT C | NOT 1 | Q = 0 |
| X = P OR Q | 0 OR 0 | X = 0 |
05 | LIST ALL EIGHT INPUT COMBINATIONS
Three binary inputs have 2 × 2 × 2 = 8 combinations. Write them in a systematic order: 000, 001, 010, 011, 100, 101, 110 and 111.
In this order, A changes after four rows, B after two and C after each row. This helps avoid missing or repeating a combination. The rows are separate cases, not a timeline: a result from one row is not carried into the next.
Do not add independent combinations for P and Q. They are calculated from the external inputs in each row.
06 | COMPLETE INTERMEDIATE COLUMNS FIRST
Fill the P column using AND, then Q using NOT, then use those two columns to calculate X using OR. The intermediate columns expose the reasoning and make mistakes easier to locate.
| A | B | C | P = A AND B | Q = NOT C | X = P OR Q |
|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 1 | 1 |
| 0 | 0 | 1 | 0 | 0 | 0 |
| 0 | 1 | 0 | 0 | 1 | 1 |
| 0 | 1 | 1 | 0 | 0 | 0 |
| 1 | 0 | 0 | 0 | 1 | 1 |
| 1 | 0 | 1 | 0 | 0 | 0 |
| 1 | 1 | 0 | 1 | 1 | 1 |
| 1 | 1 | 1 | 1 | 0 | 1 |
07 | TRACE THE CIRCUIT INTERACTIVELY
Choose A, B and C, then predict P, Q and X before tracing. The highlighted table row links the chosen values to the complete truth table. The step list explains what each gate receives.
Try 101, which gives X = 0; 110, which gives X = 1 through both routes; and 000, which gives X = 1 because NOT C is true even though A AND B is false.
08 | PARENTHESES CHANGE THE CONNECTIONS
Compare X = (A AND B) OR (NOT C) with Y = A AND (B OR (NOT C)). The same named gates appear, but their connections differ.
For Y, invert C first, combine B with that result using OR, then combine A with the OR result using AND. In other words, A is required for every route to Y.
For A = 0, B = 0, C = 0, X is 1 because NOT C supplies a true route to the final OR. Y is 0 because its final AND receives A = 0. Parentheses describe grouping, not decoration.
| Expression | First parts | Final gate | Result for 000 |
|---|---|---|---|
| (A AND B) OR (NOT C) | A AND B; NOT C | OR | 1 |
| A AND (B OR (NOT C)) | NOT C; then B OR that result | AND | 0 |
09 | WRITE AN EXPRESSION FROM A CIRCUIT
Begin at the gates closest to the inputs. Write a short expression for each intermediate output, then substitute it into the final gate’s rule.
In our diagram, P = A AND B and Q = NOT C. The final gate gives X = P OR Q. Substituting the definitions produces X = (A AND B) OR (NOT C).
For a diagram containing NAND or NOR, keep those supplied gate functions when expressing the rule, or write the full equivalent inversion with parentheses if appropriate. NOT (A AND B) and (NOT A) AND B do not describe the same connections.
Draw the circuit specified in the question without simplifying it. An equivalent shortened expression may give the same outputs while failing to reproduce the given circuit structure.
10 | TURN A REAL-WORLD STATEMENT INTO LOGIC
A fan runs when the room is hot and the window is closed, or when manual override is selected. Define A = Hot, B = WindowClosed and C = ManualOverride.
The first route is A AND B. The override is a second route, so X = (A AND B) OR C. Draw an AND for A and B, then an OR receiving its result and C.
If the input definition changes to B = WindowOpen, the first route must use NOT B. The expression becomes X = (A AND (NOT B)) OR C. Read the wording and definitions together before choosing gates.
“Both” suggests AND; “at least one” suggests OR; “exactly one” suggests XOR; “neither” suggests NOR. Check that the chosen gate matches the full condition, including what happens when both inputs are true.
11 | READ A RULE FROM A TRUTH TABLE
A truth table can also be the starting point. First inspect where the output is 1. For a two-input table, outputs 0, 1, 1, 0 in row order 00, 01, 10, 11 match XOR.
For an unfamiliar table, describe each output-1 row as a condition. A row 01 means NOT A AND B. A row 10 means A AND NOT B. OR the conditions together because either matching case should produce 1.
That gives X = ((NOT A) AND B) OR (A AND (NOT B)). If asked to identify a single gate, XOR is suitable for that table. If given the expanded expression and asked to draw it, draw its specified NOT, AND and OR structure without simplifying it.
| A | B | X |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
12 | A THREE-INPUT TABLE CAN GIVE A SIMPLE RULE
Suppose a table gives output 1 only for rows 110 and 111. A and B must both be 1; C can be either value. The rule is X = A AND B, with no dependence on C.
Compare it with output 1 only for 110. That row requires A, B and NOT C. Using two-input gates, first combine A and B, invert C, then AND those results.
The difference between one true row and two true rows tells you whether C matters. Check the proposed expression against every row, not just one example.
13 | CHECK A CIRCUIT BEFORE ACCEPTING IT
Make sure every gate receives the correct signal. A NOT gate takes one input; the other syllabus gates take two. Label external inputs, intermediate signals where helpful and the single final output.
A wire carries a value unchanged. A split feeds that same signal to more than one gate. In diagrams with crossing wires, a junction dot indicates an intentional connection; avoid ambiguous crossings in your own work.
Check all truth-table rows against the original rule. A circuit that happens to work for 111 can still fail for 001 or 101. For an explanation, name the gate, the values it receives and why its output follows.