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HARDWARE AND OPERATION | FETCH DECODE EXECUTE CYCLE

DESIGNED FOR IB EXAMINATIONS
OBJECTIVES
A1.1.5 Describe the fetch, decode and execute cycle.
  • The basic operations a CPU performs to execute a single instruction in machine language
  • The interaction between memory and registers via the three buses: address, data, control
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SECTION 1 | FETCH, DECODE AND EXECUTE CYCLE

The fetch–decode–execute cycle is the fundamental process by which a CPU carries out instructions stored in memory. Each machine language instruction is processed individually through this cycle, allowing programs to be executed step by step.

Overview of the Instruction Cycle
At its simplest, the CPU repeatedly:
  1. Fetches an instruction from memory
  2. Decodes the instruction to determine what action is required
  3. Executes the instruction

This cycle continues until the program ends or the system is shut down.
Fetch Stage
During the fetch stage, the CPU retrieves the next instruction from memory.
  • The program counter (PC) holds the address of the next instruction.
  • This address is copied into the memory address register (MAR).
  • The address is sent to main memory.
  • The instruction stored at that address is returned from memory and placed into the memory data register (MDR).
  • The instruction is then copied into the instruction register (IR).
  • The PC is incremented so it points to the next instruction in sequence.

The fetch stage ensures the CPU always knows which instruction to process next.

Decode Stage
During the decode stage, the CPU interprets the instruction.
  • The control unit (CU) examines the instruction stored in the instruction register.
  • The instruction is broken down into its components, such as the operation to be performed and any operands involved.
  • The control unit determines which hardware components are required, such as the ALU, registers, or memory.

No data processing occurs at this stage; the CPU is preparing for execution.

Execute Stage
During the execute stage, the instruction is carried out.
  • The required operation is performed, often by the arithmetic logic unit (ALU).
  • Data may be read from or written to registers or memory.
  • Results of calculations are stored in registers, such as the accumulator, or written back to memory.
  • Control signals ensure the correct movement of data and timing of operations.

The exact actions taken during execution depend on the instruction type, such as arithmetic, data transfer, or control instructions.

Continuous Operation
Once execution is complete:
  • The CPU returns to the fetch stage.
  • The next instruction is processed.
  • This cycle repeats millions or billions of times per second in modern processors.

Summary
  • The CPU executes programs by repeatedly performing the fetch–decode–execute cycle.
  • Each instruction is fetched from memory, decoded by the control unit, and executed by the appropriate CPU components.
  • This structured sequence ensures instructions are carried out accurately and in the correct order.

The fetch–decode–execute cycle describes the basic operations a CPU performs to execute a single machine language instruction, forming the foundation of all program execution.
Challenge Check: Fetch–Decode–Execute

During the fetch–decode–execute cycle, which action occurs immediately after the instruction is placed into the instruction register (IR)?

A. The arithmetic logic unit executes the instruction.
B. The control unit decodes the instruction to determine the required operation.
C. The program counter is reset to the start of the program.
D. The result of the instruction is written back to memory.

SECTION 1 | FETCH, DECODE AND EXECUTE CYCLE

The CPU communicates with memory and internal registers using three essential communication pathways known as buses. These buses allow instructions and data to be transferred and coordinated during the fetch–decode–execute cycle. Each bus has a specific role, and together they ensure correct and efficient instruction execution.

The Role of Buses in CPU Operation
A bus is a set of parallel wires used to transfer information between components of a computer system. During instruction execution, the CPU relies on buses to:
  • Specify where data is located
  • Transfer what data is required
  • Control how and when the transfer occurs

The three main buses involved are the address bus, data bus, and control bus.
Address Bus
The address bus is used to specify the location in memory that the CPU wants to access.
  • The address of a memory location is placed into the memory address register (MAR).
  • This address is sent from the CPU to main memory via the address bus.
  • The address bus is unidirectional, meaning it carries data in one direction only (from CPU to memory).

Its purpose is to identify the exact memory location involved in a read or write operation.

Data Bus
The data bus is used to transfer actual data and instructions between the CPU and memory.
  • When data is read from memory, it travels to the CPU via the data bus and is stored in the memory data register (MDR).
  • When data is written to memory, it is sent from the CPU to memory along the same bus.
  • The data bus is bidirectional, allowing data to flow in both directions.

This bus carries the contents of instructions and operands required for processing.

Control Bus
The control bus carries signals that coordinate and manage the activities of the CPU and memory.
  • Control signals specify whether a memory operation is a read or write.
  • Other signals manage timing, interrupts, and acknowledgement of data transfer.
  • These signals are generated primarily by the control unit (CU).

The control bus ensures that all components operate in the correct sequence and at the correct time.

Interaction During the Fetch–Decode–Execute Cycle
During instruction execution:
  • The address bus identifies the memory location to be accessed.
  • The data bus transfers instructions or data between memory and registers.
  • The control bus signals what operation is being performed and synchronises the process.

For example, during the fetch stage, the CPU sends an address to memory, signals a read operation, and receives the instruction via the data bus.

Summary
  • The address bus specifies where data is located.
  • The data bus transfers what data is being used.
  • The control bus coordinates how and when the transfer occurs.

The interaction between memory and registers via the address, data, and control buses allows the CPU to fetch instructions, process data, and store results accurately. These buses work together to ensure reliable communication and efficient execution within the fetch–decode–execute cycle.
Quick Check: CPU Buses

During the fetch stage of the fetch–decode–execute cycle, which statement correctly describes the role of the buses?

A. The data bus sends the memory address to RAM, and the address bus transfers the instruction to the CPU.
B. The address bus carries the memory address, the control bus signals a read operation, and the data bus returns the instruction.
C. The control bus transfers the instruction while the data bus coordinates timing signals.
D. The address bus and data bus are both bidirectional and perform identical roles.
WANT MORE HELP ON THE CPU? TRY THESE:
For a video showing the fetch decode execute cycle, click here (HurrayBanana, Published on Oct 11, 2013)
Simple animation of the fetch decode execute cycle - by future learn
Fetch–Decode–Execute Cycle | The repeated process by which the CPU retrieves an instruction from memory, interprets it, and carries it out.

Instruction | A machine language command that tells the CPU what operation to perform.

Machine Language | Low-level instructions represented in binary that the CPU can execute directly.

Fetch | The stage of the instruction cycle in which the CPU retrieves the next instruction from memory.

Decode | The stage of the instruction cycle in which the control unit interprets the instruction and determines the required actions.

Execute | The stage of the instruction cycle in which the instruction is carried out by the CPU.

Program Counter (PC) | A register that stores the memory address of the next instruction to be fetched.

Instruction Register (IR) | A register that holds the current instruction being decoded and executed.

Memory Address Register (MAR) | A register that stores the address of the memory location the CPU wants to access.

Memory Data Register (MDR) | A register that stores data or instructions being transferred between the CPU and memory.

Control Unit (CU) | The component of the CPU that manages and coordinates instruction execution by generating control signals.

Arithmetic Logic Unit (ALU) | The component of the CPU that performs arithmetic calculations and logical operations.

Bus | A set of parallel connections used to transfer data, addresses, or control signals between components of a computer system.

Address Bus | A unidirectional bus that carries the memory address from the CPU to main memory.

Data Bus | A bidirectional bus that carries data and instructions between the CPU and memory.

Control Bus | A bus that carries control signals, such as read and write commands, to coordinate operations between the CPU and memory.

Read Operation | A memory operation where data is transferred from memory to the CPU.

Write Operation | A memory operation where data is transferred from the CPU to memory.
  1. Describe the purpose of the fetch–decode–execute cycle.
  2. Explain the role of the program counter (PC) during the fetch stage.
  3. Describe how the memory address register (MAR) and memory data register (MDR) are used during the fetch stage.
  4. Explain the role of the instruction register (IR) in the instruction cycle.
  5. Describe the actions performed by the control unit during the decode stage.
  6. Explain how the arithmetic logic unit (ALU) is used during the execute stage.
  7. Describe the role of the address bus during instruction execution.
  8. Explain how the data bus and control bus work together during a memory read operation.
  9. Describe what happens if an instruction requires data from memory during the execute stage.
  10. Using a diagram, explain how registers and buses interact during the fetch stage of the fetch–decode–execute cycle.

Sample Answers – A1.1.5 Fetch–Decode–Execute Cycle

1. Purpose of the fetch–decode–execute cycle

The fetch–decode–execute cycle is the repeated process the CPU uses to retrieve instructions from memory, interpret them, and carry them out. It enables a program stored in memory to be executed one instruction at a time.

2. Role of the PC during fetch

The program counter stores the address of the next instruction to be fetched. During fetch, its value is copied into the MAR. After the instruction is fetched, the PC is incremented so it points to the next instruction in sequence, unless a control instruction changes it.

3. Use of MAR and MDR during fetch

The MAR holds the address of the memory location containing the next instruction. The CPU sends this address to memory. The instruction retrieved from memory is transferred via the data bus into the MDR, where it is held temporarily before being copied into the IR.

4. Role of the IR

The instruction register holds the current instruction being processed. The control unit reads the instruction in the IR during decoding to determine which operation to perform and how to execute it.

5. Control unit actions during decode

During decode, the control unit interprets the instruction stored in the IR, identifies the operation and required operands, and generates control signals to prepare the CPU components (such as registers, ALU, and memory) for execution.

6. Use of the ALU during execute

During execute, the ALU performs arithmetic operations (such as addition) and logical operations (such as comparisons). It processes values from registers and stores the result in a register such as the accumulator or writes it back to memory as required.

7. Role of the address bus

The address bus carries the address held in the MAR from the CPU to main memory. This identifies the exact memory location the CPU wants to read from or write to.

8. Data bus and control bus during a read operation

The control bus carries a read signal from the control unit to memory, indicating that data should be retrieved. The data bus then transfers the requested instruction or data from memory back to the CPU, typically into the MDR.

9. When an instruction needs data from memory during execute

If execution requires data not currently in registers or cache, the CPU places the required address into the MAR, signals a read operation, and retrieves the data into the MDR. The data is then transferred to the appropriate register so the ALU or other unit can use it.

10. Registers and buses during fetch (diagram explanation)

The PC contains the address of the next instruction. This address is copied to the MAR and sent to memory via the address bus. The control unit sends a read signal on the control bus. The instruction is returned from memory on the data bus into the MDR and then copied into the IR.

Example text diagram:
PC → MAR → (Address Bus) → Memory
CU: READ → (Control Bus) → Memory
Memory → (Data Bus) → MDR → IR

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