HARDWARE AND OPERATION | FUNCTIONS OF THE CPU
DESIGNED FOR IB EXAMINATIONS
OBJECTIVES
A1.1.1 Describe the functions and interactions of the main CPU components.
A1.1.1 Describe the functions and interactions of the main CPU components.
- Units: arithmetic logic unit (ALU), control unit (CU)
- Registers: instruction register (IR), program counter (PC), memory address register (MAR), memory data register (MDR), accumulator (AC)
- Buses: address, data, control
- Processors: single core processor, multi-core processor, co-processors
- A diagrammatic representation of the relationship between the specified CPU components
SECTION 1 | ALU UNITS
The Central Processing Unit (CPU) is the main component of a computer that performs most of the processing. It retrieves instructions from memory, decodes and executes them, and manages the flow of data in and out of the computer. The CPU is responsible for carrying out basic arithmetic, logical, and input/output operations and acts as the "brain" of the computer, making decisions based on the instructions it receives.
Arithmetic Logic Unit (ALU)
The arithmetic logic unit (ALU) is responsible for performing all arithmetic and logical operations within the CPU.
Its main functions include:
The ALU operates on data provided by registers and returns the result to a register, often the accumulator. Although the ALU is powerful, it does not decide when operations occur; it simply performs operations when instructed.
Control Unit (CU)
The control unit (CU) manages and coordinates the activities of the CPU.
Its main functions include:
The CU ensures that instructions are executed in the correct sequence and that each component of the CPU performs its role at the appropriate time. It does not process data itself but acts as the “director” of the CPU.
Relationship Between the ALU and CU
The ALU and CU work closely together:
Together, the ALU and CU form the core functional units of the CPU, enabling it to execute programs accurately and efficiently.
Arithmetic Logic Unit (ALU)
The arithmetic logic unit (ALU) is responsible for performing all arithmetic and logical operations within the CPU.
Its main functions include:
- Performing arithmetic operations such as addition, subtraction, multiplication, and division.
- Performing logical operations such as AND, OR, and NOT.
- Carrying out comparison operations (for example, checking if one value is greater than another).
- Producing results that may be stored in registers or sent back to memory.
The ALU operates on data provided by registers and returns the result to a register, often the accumulator. Although the ALU is powerful, it does not decide when operations occur; it simply performs operations when instructed.
Control Unit (CU)
The control unit (CU) manages and coordinates the activities of the CPU.
Its main functions include:
- Fetching instructions from memory.
- Decoding instructions to determine what actions are required.
- Controlling the movement of data between the CPU, memory, and input/output devices.
- Sending control signals to other CPU components, including the ALU and registers.
The CU ensures that instructions are executed in the correct sequence and that each component of the CPU performs its role at the appropriate time. It does not process data itself but acts as the “director” of the CPU.
Relationship Between the ALU and CU
The ALU and CU work closely together:
- The CU interprets instructions and issues control signals.
- The ALU performs the calculations or logical decisions specified by those instructions.
- Results are then stored or passed on as directed by the CU.
Together, the ALU and CU form the core functional units of the CPU, enabling it to execute programs accurately and efficiently.
SECTION 2 | REGISTERS
Registers are small, high-speed storage locations within the CPU. They temporarily hold data, instructions, and addresses that are currently being used, allowing the CPU to operate efficiently during the fetch–decode–execute cycle.
The main registers required for this section are the instruction register (IR), program counter (PC), memory address register (MAR), memory data register (MDR), and accumulator (AC).
Instruction Register (IR)
The instruction register (IR) stores the current instruction that has been fetched from memory.
Program Counter (PC)
The program counter (PC) stores the memory address of the next instruction to be fetched.
Memory Address Register (MAR)
The memory address register (MAR) stores the address of the memory location that is about to be accessed.
Memory Data Register (MDR)
The memory data register (MDR) stores data that is being transferred between the CPU and memory.
Accumulator (AC)
The accumulator (AC) stores intermediate results of arithmetic and logical operations.
Role of Registers in the Fetch–Decode–Execute Cycle
During program execution:
Registers enable fast and efficient instruction execution by reducing the need for constant access to main memory
The main registers required for this section are the instruction register (IR), program counter (PC), memory address register (MAR), memory data register (MDR), and accumulator (AC).
Instruction Register (IR)
The instruction register (IR) stores the current instruction that has been fetched from memory.
- It holds the instruction while it is being decoded and executed.
- The control unit reads the contents of the IR to determine which operation should be performed.
- Only one instruction is stored in the IR at a time.
Program Counter (PC)
The program counter (PC) stores the memory address of the next instruction to be fetched.
- After an instruction is fetched, the PC is incremented to point to the following instruction.
- If a jump or branch instruction occurs, the PC may be updated to a different address.
- It ensures that instructions are executed in the correct sequence.
Memory Address Register (MAR)
The memory address register (MAR) stores the address of the memory location that is about to be accessed.
- It holds addresses for both read and write operations.
- The address stored in the MAR is sent to memory via the address bus.
- It is used whenever data or instructions need to be fetched from or stored in memory.
Memory Data Register (MDR)
The memory data register (MDR) stores data that is being transferred between the CPU and memory.
- When data is read from memory, it is placed in the MDR.
- When data is written to memory, it is first placed in the MDR before being sent.
- It temporarily holds instructions or data during memory operations.
Accumulator (AC)
The accumulator (AC) stores intermediate results of arithmetic and logical operations.
- It is closely linked to the ALU.
- Results produced by the ALU are often stored in the accumulator.
- The accumulator may also hold one of the operands for an ALU operation.
Role of Registers in the Fetch–Decode–Execute Cycle
During program execution:
- The PC identifies the next instruction.
- The MAR holds the address of that instruction.
- The instruction is transferred via the MDR and stored in the IR.
- The CU decodes the instruction.
- The ALU processes data using values stored in registers such as the accumulator.
Registers enable fast and efficient instruction execution by reducing the need for constant access to main memory
SECTION 2 | BUSES
Whilst there are many different types of computer architecture in current technology, John von Neumann was a pioneer of the principle that modern processors follow. This section closely relates to the basic Von Neumann concept of CPU architecture.
THE SYSTEM BUS
The system bus refers to the method in which data and signals are transferred throughout a computer system. Data travels through various medium such as cables, ribbons and tracks on a circuit board. Where processor fundamentals are concerned there are three different Bus systems each with their own purpose.
THE ADDRESS BUS
The address bus, as its name suggest simply carries an address. This address is the address(location) that needs to be accessed from the memory. If we think of the memory as being like a very large spreadsheet containing thousands of cells and each cell has its own unique address. The address bus carries the address location of a specific cell within the memory to be accessed. Earlier computers had address buses that were only 8 wires wide, this only allowed the machine to transfer 1 byte (8 bits) at a time, which limited the maximum amount of address locations that could be represented to 256 locations (with 1 byte we can represent between 0 and 255), so adding more that 256 memory locations to an 8 bit computer would have been very inefficient.
Many modern computers are 64 bit, meaning the address bus is 64 wires wide, allowing address locations of between 0 and 18,446,744,073,709,551,615 (18 Quintillion) to be accessed in a single request, although modern computers may not contain this amount of memory locations.
The Address Bus is unidirectional, meaning it is a one way system and only carries the location of the address to be accessed from the processor to the memory, the data from that memory location is then transfers through the Data Bus.
THE DATA BUS
THE Data Bus is bi-directional (meaning that data can flow two ways) and is responsible for transporting data between the memory, the processor and and I/O (input/output) devices. The size of the Data Bus varies between machines, however it is efficient to have a Data Bus at least equivalent to the size of a Word. A word is the number of bytes that the system will handle in one go, for example 16, 32 or 64 bits. If the computer system uses 64 bits as a word and the Data Bus is only 32 wires wide, then the word would need to be transmitted through the data bus as 2 separate signals, thus making it inefficient. The size of the Data Bus does not need to be the same size as the Address Bus.
THE CONTROL BUS
The Control Bus is bi-directional (meaning that data can flow two ways) and is responsible for transmitting signals between various components. The Control Bus is generally only 8 wires wide as it carries signals rather than larges combinations of data representations. It is primarily tasked with carrying timing signals from the system clock, aiding the synchronisation of tasks.
The clock speed is a major factor in determining the overall speed of the computer, it can be seen that on every tick of the clock an action is performed, the more times per second the clock ticks the more actions are performed.
As can be seen in the system bus diagram the Data Bus is not directly connected to any input or output devices, it is connected to a separate I/O interface or device controller.
The address bus, as its name suggest simply carries an address. This address is the address(location) that needs to be accessed from the memory. If we think of the memory as being like a very large spreadsheet containing thousands of cells and each cell has its own unique address. The address bus carries the address location of a specific cell within the memory to be accessed. Earlier computers had address buses that were only 8 wires wide, this only allowed the machine to transfer 1 byte (8 bits) at a time, which limited the maximum amount of address locations that could be represented to 256 locations (with 1 byte we can represent between 0 and 255), so adding more that 256 memory locations to an 8 bit computer would have been very inefficient.
Many modern computers are 64 bit, meaning the address bus is 64 wires wide, allowing address locations of between 0 and 18,446,744,073,709,551,615 (18 Quintillion) to be accessed in a single request, although modern computers may not contain this amount of memory locations.
The Address Bus is unidirectional, meaning it is a one way system and only carries the location of the address to be accessed from the processor to the memory, the data from that memory location is then transfers through the Data Bus.
THE DATA BUS
THE Data Bus is bi-directional (meaning that data can flow two ways) and is responsible for transporting data between the memory, the processor and and I/O (input/output) devices. The size of the Data Bus varies between machines, however it is efficient to have a Data Bus at least equivalent to the size of a Word. A word is the number of bytes that the system will handle in one go, for example 16, 32 or 64 bits. If the computer system uses 64 bits as a word and the Data Bus is only 32 wires wide, then the word would need to be transmitted through the data bus as 2 separate signals, thus making it inefficient. The size of the Data Bus does not need to be the same size as the Address Bus.
THE CONTROL BUS
The Control Bus is bi-directional (meaning that data can flow two ways) and is responsible for transmitting signals between various components. The Control Bus is generally only 8 wires wide as it carries signals rather than larges combinations of data representations. It is primarily tasked with carrying timing signals from the system clock, aiding the synchronisation of tasks.
The clock speed is a major factor in determining the overall speed of the computer, it can be seen that on every tick of the clock an action is performed, the more times per second the clock ticks the more actions are performed.
As can be seen in the system bus diagram the Data Bus is not directly connected to any input or output devices, it is connected to a separate I/O interface or device controller.
QUICK QUESTION
What is Binary?
A) A number system that uses digits 0 through 9
B) A number system that uses digits 0 and 1
C) A method for representing negative numbers
D) An operation that moves bits left or right within a binary number
SECTION 4 | PROCESSORS
A processor is the component of a computer system responsible for executing program instructions. Different processor designs affect how instructions are executed and how efficiently tasks are handled. The main processor types relevant at this level are single core processors, multi-core processors, and co-processors.
Single Core Processor
A single core processor contains one processing unit capable of executing one instruction at a time.
Multi-Core Processor
A multi-core processor contains two or more independent processing cores on a single chip.
Co-Processors
A co-processor is a specialised processor designed to assist the main CPU by handling specific types of tasks.
Single Core Processor
A single core processor contains one processing unit capable of executing one instruction at a time.
- All program instructions are processed sequentially.
- If multiple programs are running, the processor rapidly switches between tasks using time slicing, creating the illusion of multitasking.
- Performance is limited by the speed of the single core, as only one instruction stream can be executed at any given moment.
Multi-Core Processor
A multi-core processor contains two or more independent processing cores on a single chip.
- Each core can execute instructions simultaneously.
- Tasks can be divided across multiple cores, improving overall performance.
- Supports true parallel processing rather than simple time sharing.
Co-Processors
A co-processor is a specialised processor designed to assist the main CPU by handling specific types of tasks.
- It operates alongside the main processor.
- It is optimised for particular operations, improving speed and efficiency.
- Common tasks include graphics rendering, mathematical calculations, and artificial intelligence processing.
SECTION 4 | DIAGRAMATIC REPRESENTATION
A diagrammatic representation of the CPU shows how its main components are connected and how they interact during instruction execution. Understanding this relationship is essential for explaining how the fetch–decode–execute cycle operates.
Overview of the Diagram
The diagram illustrates both the physical separation of components and the flow of data and control signals between them.
Overview of the Diagram
- A typical CPU diagram includes the following components:
- Arithmetic logic unit (ALU)
- Control unit (CU)
- Registers: program counter (PC), instruction register (IR), memory address register (MAR), memory data register (MDR), accumulator (AC)
- Buses: address bus, data bus, control bus
- Main memory (shown externally to the CPU)
The diagram illustrates both the physical separation of components and the flow of data and control signals between them.
Relationships Between Components
Purpose of the Diagram
The diagram helps to:
A clear diagrammatic representation supports accurate explanations of processor operation and is frequently required in assessments to accompany written descriptions.
- The control unit (CU) coordinates all activities within the CPU by sending control signals to the ALU, registers, and memory.
- The program counter (PC) provides the address of the next instruction, which is copied to the memory address register (MAR).
- The address in the MAR is sent to main memory via the address bus.
- The fetched instruction or data is transferred from memory to the memory data register (MDR) via the data bus.
- The instruction is then copied from the MDR into the instruction register (IR) for decoding.
- The arithmetic logic unit (ALU) performs calculations or logical operations using data from registers, often storing intermediate or final results in the accumulator (AC).
- The control bus carries control signals, such as read and write commands, from the CU to memory and other components.
Purpose of the Diagram
The diagram helps to:
- Visualise how instructions and data move through the CPU.
- Show the role of each register at different stages of execution.
- Demonstrate how the CU and ALU interact to carry out instructions.
- Clarify the function of buses in linking internal CPU components to memory.
A clear diagrammatic representation supports accurate explanations of processor operation and is frequently required in assessments to accompany written descriptions.
Arithmetic Logic Unit (ALU) | The part of the CPU responsible for carrying out arithmetic operations (such as addition and subtraction) and logical operations (such as comparisons and Boolean logic).
Accumulator (AC) | A register used to store intermediate results produced by the arithmetic logic unit during processing.
Address Bus | A set of wires that carries memory addresses from the CPU to main memory, indicating where data should be read from or written to.
Control Bus | A set of wires that carries control signals from the control unit to other components, such as read, write, and clock signals.
Control Unit (CU) | The component of the CPU that manages and coordinates all activities by fetching, decoding, and controlling the execution of instructions.
Co-Processor | A specialised processor that works alongside the main CPU to handle specific tasks more efficiently, such as graphics processing or mathematical calculations.
Data Bus | A set of wires that carries actual data and instructions between the CPU, memory, and input/output devices.
Instruction Register (IR) | A register that stores the current instruction being decoded and executed by the CPU.
Memory Address Register (MAR) | A register that holds the address of the memory location that is about to be accessed.
Memory Data Register (MDR) | A register that temporarily stores data being transferred between the CPU and main memory.
Multi-Core Processor | A processor that contains two or more independent cores, allowing multiple instructions or tasks to be executed simultaneously.
Processor | The hardware component responsible for executing program instructions and controlling computer operations.
Program Counter (PC) | A register that stores the memory address of the next instruction to be fetched and executed.
Registers | Small, high-speed storage locations within the CPU used to hold data, instructions, and addresses currently being processed.
Single Core Processor | A processor with only one core that can execute one instruction at a time, using time slicing to manage multiple tasks.
Von Neumann Architecture | A computer architecture model in which instructions and data are stored in the same memory and accessed using shared buses.
Accumulator (AC) | A register used to store intermediate results produced by the arithmetic logic unit during processing.
Address Bus | A set of wires that carries memory addresses from the CPU to main memory, indicating where data should be read from or written to.
Control Bus | A set of wires that carries control signals from the control unit to other components, such as read, write, and clock signals.
Control Unit (CU) | The component of the CPU that manages and coordinates all activities by fetching, decoding, and controlling the execution of instructions.
Co-Processor | A specialised processor that works alongside the main CPU to handle specific tasks more efficiently, such as graphics processing or mathematical calculations.
Data Bus | A set of wires that carries actual data and instructions between the CPU, memory, and input/output devices.
Instruction Register (IR) | A register that stores the current instruction being decoded and executed by the CPU.
Memory Address Register (MAR) | A register that holds the address of the memory location that is about to be accessed.
Memory Data Register (MDR) | A register that temporarily stores data being transferred between the CPU and main memory.
Multi-Core Processor | A processor that contains two or more independent cores, allowing multiple instructions or tasks to be executed simultaneously.
Processor | The hardware component responsible for executing program instructions and controlling computer operations.
Program Counter (PC) | A register that stores the memory address of the next instruction to be fetched and executed.
Registers | Small, high-speed storage locations within the CPU used to hold data, instructions, and addresses currently being processed.
Single Core Processor | A processor with only one core that can execute one instruction at a time, using time slicing to manage multiple tasks.
Von Neumann Architecture | A computer architecture model in which instructions and data are stored in the same memory and accessed using shared buses.
1: Describe the role of the arithmetic logic unit (ALU) within the central processing unit.
2: Explain how the control unit (CU) coordinates the activities of the CPU during instruction execution.
3: Describe the function of the program counter (PC) and explain how its value changes during normal program execution.
4: Explain the role of the instruction register (IR) in the fetch–decode–execute cycle.
5: Describe how the memory address register (MAR) and memory data register (MDR) are used together when accessing main memory.
6: Explain the purpose of the accumulator (AC) and how it interacts with the arithmetic logic unit.
7: Describe the function of each of the three buses and explain why all three are required in a computer system.
8: Compare a single core processor with a multi-core processor in terms of instruction execution and performance.
9: Explain the role of a co-processor and describe one advantage of using co-processors in modern computer systems.
10: Using a diagram, explain the relationship between the main CPU components during the fetch stage of the fetch–decode–execute cycle.
2: Explain how the control unit (CU) coordinates the activities of the CPU during instruction execution.
3: Describe the function of the program counter (PC) and explain how its value changes during normal program execution.
4: Explain the role of the instruction register (IR) in the fetch–decode–execute cycle.
5: Describe how the memory address register (MAR) and memory data register (MDR) are used together when accessing main memory.
6: Explain the purpose of the accumulator (AC) and how it interacts with the arithmetic logic unit.
7: Describe the function of each of the three buses and explain why all three are required in a computer system.
8: Compare a single core processor with a multi-core processor in terms of instruction execution and performance.
9: Explain the role of a co-processor and describe one advantage of using co-processors in modern computer systems.
10: Using a diagram, explain the relationship between the main CPU components during the fetch stage of the fetch–decode–execute cycle.
Sample Answers – A1.1.1 CPU Components
1. Arithmetic Logic Unit (ALU)
The arithmetic logic unit performs arithmetic calculations and logical operations within the CPU. It processes data taken from registers and produces results that are stored in registers such as the accumulator.
2. Control Unit (CU)
The control unit coordinates CPU activity by fetching and decoding instructions and issuing control signals. These signals manage data movement between registers, the ALU, memory, and input/output devices, ensuring instructions are executed in the correct order.
3. Program Counter (PC)
The program counter stores the address of the next instruction to be fetched. After each instruction is fetched, the PC is incremented so that execution continues sequentially, unless a jump or branch instruction changes its value.
4. Instruction Register (IR)
The instruction register stores the instruction currently being decoded and executed. The control unit reads the contents of the IR to determine which operation the CPU must perform.
5. Memory Address Register (MAR) and Memory Data Register (MDR)
The MAR stores the address of the memory location to be accessed and sends this address via the address bus. The MDR stores the data being transferred to or from memory via the data bus during read or write operations.
6. Accumulator (AC)
The accumulator stores intermediate results of arithmetic and logical operations. It works closely with the ALU by holding operands and results during processing.
7. Address, Data, and Control Buses
The address bus carries memory addresses, the data bus carries data and instructions, and the control bus carries control signals such as read and write. All three are required to correctly identify locations, transfer data, and coordinate operations.
8. Single Core vs Multi-Core Processors
A single core processor can execute one instruction stream at a time, relying on time slicing for multitasking. A multi-core processor contains multiple cores that can execute instructions simultaneously, improving performance through parallel processing.
9. Co-Processor
A co-processor is a specialised processor that assists the main CPU by handling specific tasks. This improves performance and efficiency by offloading complex or repetitive operations from the CPU.
10. Fetch Stage Relationships
During the fetch stage, the PC value is copied to the MAR and sent to memory via the address bus. The control unit issues a read signal on the control bus, and the instruction is transferred from memory to the MDR via the data bus before being placed into the IR.
COMING SOON
A1.1 COMPUTER HARDWARE AND OPERATION
➩ 1.1.1 FUNCTIONS OF THE CPU
☐ 1.1.2 ROLE OF THE GPU
☐ 1.1.3 CPU VS GPU
☐ 1.1.4 PURPOSE AND TYPES OF PRIMARY MEMORY
☐ 1.1.5 FETCH, DECODE AND EXECUTE CYCLE
☐ 1.1.6 PIPELINING IN MULTICORE ARCHITECTURES
☐ 1.1.7 SECONDARY MEMORY STORAGE
☐ 1.1.8 CONCEPTS OF DATA COMPRESSION
☐ 1.1.9 CLOUD COMPUTING
A1.2 DATA REPRESENTATION AND COMPUTER LOGIC
☐ 1.2.1 REPRESENTING DATA
☐ 1.2.2 HOW BINARY IS USED TO STORE DATA
☐ 1.2.3 LOGIC GATES
☐ 1.2.4 TRUTH TABLES, CIRCUITS, EXPRESSIONS AND K MAPS
☐ 1.2.5 LOGIC CIRCUIT DIAGRAMS - COMING SOON
A1.3 OPERATING SYSTEMS AND CONTROL SYSTEMS
☐ 1.3.1 ROLE OF OPERATING SYSTEMS
☐ 1.3.2 FUNCTIONS OF OPERATING SYSTEMS
☐ 1.3.3 APPROACHES TO SCHEDULING
☐ 1.3.4 INTERUPT HANDLING
☐ 1.3.5 MULTITASKING
☐ 1.3.6 CONTROL SYSTEM COMPONENTS
☐ 1.3.7 CONTROL SYSTEM APPLICATIONS
➩ 1.1.1 FUNCTIONS OF THE CPU
☐ 1.1.2 ROLE OF THE GPU
☐ 1.1.3 CPU VS GPU
☐ 1.1.4 PURPOSE AND TYPES OF PRIMARY MEMORY
☐ 1.1.5 FETCH, DECODE AND EXECUTE CYCLE
☐ 1.1.6 PIPELINING IN MULTICORE ARCHITECTURES
☐ 1.1.7 SECONDARY MEMORY STORAGE
☐ 1.1.8 CONCEPTS OF DATA COMPRESSION
☐ 1.1.9 CLOUD COMPUTING
A1.2 DATA REPRESENTATION AND COMPUTER LOGIC
☐ 1.2.1 REPRESENTING DATA
☐ 1.2.2 HOW BINARY IS USED TO STORE DATA
☐ 1.2.3 LOGIC GATES
☐ 1.2.4 TRUTH TABLES, CIRCUITS, EXPRESSIONS AND K MAPS
☐ 1.2.5 LOGIC CIRCUIT DIAGRAMS - COMING SOON
A1.3 OPERATING SYSTEMS AND CONTROL SYSTEMS
☐ 1.3.1 ROLE OF OPERATING SYSTEMS
☐ 1.3.2 FUNCTIONS OF OPERATING SYSTEMS
☐ 1.3.3 APPROACHES TO SCHEDULING
☐ 1.3.4 INTERUPT HANDLING
☐ 1.3.5 MULTITASKING
☐ 1.3.6 CONTROL SYSTEM COMPONENTS
☐ 1.3.7 CONTROL SYSTEM APPLICATIONS
